In a conventional CMOS process, in order to improve a performance of a device, high k (dielectric constant) gate dielectric materials and metal gate materials are commonly used. Researches show that high k dielectric materials instead of silicon oxide as a gate dielectric of a CMOS device have a dielectric constant higher than that of silicon oxide, so that a gate capacitance may be increased without decreasing a physical thickness of the CMOS device. Therefore, an equivalent oxide thickness (EOT) may be decreased without increasing leakage, thus improving the performance of the device.
However, some problems need to be improved in a process of using high k gate dielectric materials and metal gate materials. For example, an interface state is high, the EOT needs to be further decreased, and a work function needs to be adjusted. However, a dielectric constant of an interfacial layer formed during annealing is low, and a thickness of the interfacial layer is about 1 nm, thus preventing the EOT from being further decreased and preventing the performance of the device from being further improved. As for the work function, a use of TiN/HfO2 may meet a requirement of PMOS (the work function being about 5.2 eV). However, there is no suitable technology for adjusting the work function of the semiconductor structure without introducing a capping layer to meet a requirement of NMOS (the work function being about 4.2 eV). In addition, a thermal stability of high k dielectrics is always a focus. Hafnium based gate dielectric has become a useful dielectric material. However, hafnium oxide may be easily crystallized at about 500° C., thus increasing a device leakage and deteriorating the performance of the device.